Event-Driven Architectures for Ultra-Low-Latency Systems: Design Principles, Reference Patterns, and Evaluation

Abstract

Ultra-low-latency, event-driven systems have strict end-to-end latency demands in the range of microseconds or sub-milliseconds for applications in high-frequency trading, augmented realities, teleoperation, and real-time machine learning inference. Current applications require not only reductions in median latency performance, but also tight control on tail latency to meet service-level objectives and maintain operational safety. Recent advances in kernel-bypass networking (DPDK, AF_XDP), persistent RDMA semantics, FPGAs as fabrics, and deterministic scheduling provide powerful ways to achieve these demands, but there does not yet exist an integrated framework that covers all of these techniques. This article builds on five years of systems research and organizes the findings into a usable taxonomy that maps sources of latency, namely: network traversal, kernel overheads, serialization, scheduling delays, and distributed state management, to architectural levers and supporting systems. Three example architectures are shown: a single-node user-space architecture, a rack-scale PCIe/FPGA architecture, and a DRAM-assisted architecture. It also presents application-level implementation patterns for users to achieve similar latency outcomes, focusing on zero-copy paths, NIC offload, and placement that preserves locality. It also gives reproducible evaluation techniques associated with the implementation patterns in this development. Finally, case study examples from high-frequency trading and edge-based machine learning inference are presented in which single-digit microsecond latency is feasible while also explaining fundamental trade-offs among latency, maintainability, and hardware specialization.