Electrical Resistivity and Minority Carrier Lifetime Distribution in Directional Solidification of Silicon Ingot

Abstract

In this work, the main electrical wafer qualities were studied through resistivity and minority carrier lifetime variation, as a function of wafer position. The multi-crystalline silicon ingot was grown by directional solidification using the so-called -Heat Exchanger Method (HEM). The solid-liquid interface moves upwards from the bottom to top of the crucible. The growth rate is controlled so as to favour the growth of a high quality crystal structure by finely adjusting the position of the heat exchanger -HEX -block and the heater temperature value. The goal is to obtain vertically aligned grains which confirm a good directional growth. The achieved analyses were conducted by using the quasi-stationary photo conductance (QSSPC) and the four probe techniques.  The ingot produced exhibits uniform large grain morphology with vertically-oriented grain boundaries. The resistivity for corner and center brick’s present a maximum value of 2.3 Ω.cm and 1.69 Ω.cm respectively, after half (50%) of growth, and a minimal value in the first and final stages of solidification. In the beginning of growth, the initial minority carrier lifetime value is 3.23µs and 3.96µs for corner and center bricks respectively. Both lifetimes values grow to the maximum with 8.55µs and 14.05µs for corner and center bricks respectively, at the middle solidification position. The variation of electrical resistivity and minority carrier lifetime is probably affected by the impurity concentration, structural defects and grain structure.