Efficient FPGA Implementation of Visual Cryptography Using AES Algorithm and Share Generation Technique
DOI:
https://doi.org/10.22399/ijcesen.3070Keywords:
AES Algorithm, Share Generation Technique, Visual CryptographyAbstract
Visual Cryptography is the latest secure communication technique where the secured data is always in the form of an image from which a finite number of shares are generated using a mathematical model. At the receiver side, the secret image is generated from these shares using a reverse mathematical approach. In this Article, Efficient FPGA Implementation of Visual Cryptography using AES Algorithm and Share Generation Technique is proposed. To increase security, AES algorithm is used for encoding, and is further subjected to share generation, the entire architectural level is designed to achieve optimum utilization without affecting the reconstruction quality, which is then coded using VHDL language and implemented on Zybo Z7-10 FPGA board. The comparison results show that the proposed technique is better in terms of both hardware parameters and reconstructed image quality.
References
[1] Maazouz, M., Toubal, A., Bengherbia, B., Houhou, O., & Batel, N. (2022). FPGA implementation of a chaos-based image encryption algorithm. Journal of King Saud University – Computer and Information Sciences, 34, 9926–9941.
[2] Morales-Sandoval, M., Rodriguez Flores, L. A., Cumplido, R., Garcia-Hernandez, J. J., Feregrino, C., & Algredo, I. (2020). A compact FPGA-based accelerator for curve-based cryptography in wireless sensor networks. Journal of Sensors, 2021, Article ID 8860413. https://doi.org/10.1155/2021/8860413
[3] Ricci, S., Dobias, P., Malina, L., Hajny, J., & Jedlicka, P. (2024). Hybrid keys in practice: Combining classical, quantum and post-quantum cryptography. IEEE Access, 12, 23206–23219.
[4] Bonny, T., & Al Nassan, W. (2024). Neuro Chaos Crypt: Revolutionizing chaotic-based cryptosystem with artificial neural networks—A comparison with traditional cryptosystems. IEEE Access, 4. https://doi.org/10.1109/ACCESS.2024.3395527
[5] Kumar, S., Kumar, D., Lamkuche, H., Sharma, V. S., Alkahtani, H. K., Elsadig, M., & Bivi, M. A. (2024). SHC: 8-bit compact and efficient S-Box structure for lightweight cryptography. IEEE Access, 12, 39430–39449.
[6] Rupanagudi, S. R., Bhat, V. G., Anushree, R., & Kavitha, Y. (2016). A novel and highly secure encryption methodology using a combination of AES and visual cryptography. In 2016 International Conference on Advances in Computing, Communications and Informatics (ICACCI) (pp. 1682–1688). IEEE.
[7] Goel, A., & Chaudhari, K. (2016). FPGA implementation of a novel technique for selective image encryption. In 2nd International Conference on Frontiers of Signal Processing (ICFSP) (pp. 15–19). IEEE.
[8] Gaur, N., Mehra, A., & Kumar, P. (2018). Enhanced AES architecture using extended set ALU at 28nm FPGA. In 5th International Conference on Signal Processing and Integrated Networks (SPIN) (pp. 437–440). IEEE.
[9] Chen, S., Hu, W., & Li, Z. (2019). High performance data encryption with AES implementation on FPGA. In IEEE 5th International Conference on Big Data Security on Cloud (Big Data Security), High Performance and Smart Computing (HPSC), Intelligent Data and Security (IDS) (pp. 149–153). IEEE.
[10] Bu, A., Dai, W., Lu, M., Cai, H., & Shan, W. (2018). Correlation-based electromagnetic analysis attack using Haar wavelet reconstruction with low-pass filtering on an FPGA implementation of AES. In 17th IEEE International Conference on Trust, Security and Privacy in Computing and Communications / 12th IEEE International Conference on Big Data Science and Engineering (pp. 1897–1900). IEEE.
[11] Gangadari, B. R., & Ahamed, S. R. (2015). FPGA implementation of compact S-Box for AES algorithm using composite field arithmetic. In Annual IEEE India Conference (INDICON) (pp. 1–5). IEEE.
[12] Shankar, K., & Eswaran, P. (2017). RGB-based multiple share creation in visual cryptography with aid of elliptic curve cryptography. China Communications, 14(2), 118–130.
[13] Jia, X., Wang, D., Ni, D., & Zhang, C. (2018). Collaborative visual cryptography schemes. IEEE Transactions on Circuits and Systems for Video Technology, 28(5), 1056–1070.
[14] Porwal, P., Panda, A. K., Sarad, H., Hritvij, H., & Sapna, P. J. (2022). Security system based on image encryption using fractal matrix method. International Research Journal of Modernization in Engineering Technology and Science (IRJMETS), 4(7), e-ISSN: 2582-5208.
[15] Ahmad, L., Al-Sabha, R., & Al-Haj, A. (2021). Design and implementation of a secure QR payment system based on visual cryptography. In 7th International Conference on Information Management (ICIM). IEEE.
[16] Yan, B., Xiang, Y., & Hua, G. (2019). Improving the visual quality of size-invariant visual cryptography for grayscale images: An analysis-by-synthesis (AbS) approach. IEEE Transactions on Image Processing, 28(2), 681–694.
[17] ,Stallings, W. (2014). Cryptography and network security: Principles and practice. Prentice Hall.
[18] Roth, C. H. (Jr.). (1992). Fundamentals of logic design (1st ed.). Jaico Publishing House.
[19] Bakeva, V., Dimitrova, V., & Kostadinoski, M. (2014). Pseudo random sequence generators based on the parastrophic quasigroup transformation. In ICT Innovations 2014 (pp. 125–134). Springer.
[20] Panda, A. K., Rajput, P., & Shukla, B. (2012). FPGA implementation of 8, 16 and 32-bit LFSR with maximum length feedback polynomial using VHDL. In International Conference on Communication Systems and Network Technologies (pp. 769–773). IEEE.
[21] Sasaki, M., & Watanabe, Y. (2018). Visual secret sharing schemes encrypting multiple images. IEEE Transactions on Information Forensics and Security, 13(2), 482–491.
[22] Karolin, M., & Meyyappan, T. (2019). Secret multiple share creation with color images using visual cryptography. In IEEE Advance Technology of Humanity. https://doi.org/10.1109
[23] Sikka, P., Asati, A. R., & Shekhar, C. (2020). Speed optimal FPGA implementation of the encryption algorithms for telecom applications. Microprocessors and Microsystems, 79, 103324. https://doi.org/10.1016/j.micpro.2020.103324
[24] Garipcan, A. M., & Erdem, E. (2021). FPGA implementation and statistical analysis of a high-speed, and low-area TRNG based on an AES S-box post-processing technique. ISA Transactions. https://doi.org/10.1016/j.isatra.2021.01.054
[25] Roth, C. H. (Jr.). (2006). Digital system design using VHDL. Cengage Learning.
Gonzalez, R. C., Woods, R. E., & Eddins, S. L. (2009). Digital image processing using MATLAB (2nd ed.). Gatesmark Publishing.
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