Enhancing Network-On-Chip Performance: Advanced Mmu Techniques For Lower Latency And Higher Bandwidth
DOI:
https://doi.org/10.22399/ijcesen.2556Keywords:
Network-on-Chip (NoC), Memory Management Unit, Latency Optimization, Bandwidth Utilization, TLB CachingAbstract
With the increasing complexity of high-performance computing systems, Network-on-Chip (NoC) architectures face critical performance bottlenecks due to memory management latency and inefficient bandwidth utilization. This research presents a novel, mathematically rigorous framework for optimizing NoC performance through advanced Memory Management Unit (MMU) techniques, specifically Translation Lookaside Buffer (TLB) caching and hybrid address mapping. The study develops symbolic models of latency and bandwidth as optimization functions, accounting for memory translation delays and dynamic workload patterns. Using discrete-event simulation based on analytically defined traffic and MMU behavior assumptions, we evaluate performance across various configurations. Our results indicate that hybrid address mapping yields up to 30.7% latency reduction and 32% bandwidth efficiency gain, while TLB caching provides 26.1% latency improvement and 27.3% increased throughput. These findings, derived under theoretical constraints, demonstrate the potential of MMU-level optimizations for significantly enhancing NoC system performance. The proposed model serves as a foundational tool for future adaptive and scalable memory management strategies in edge computing, real-time systems, and data-intensive applications.
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