V VENKATA SAI RAGHAVA; M RAVI KUMAR. Digital System Design of FPGA – Based UART Protocol Using Verilog HDL. International Journal of Computational and Experimental Science and Engineering, [S. l.], v. 11, n. 3, 2025. DOI: 10.22399/ijcesen.3306. Disponível em: https://www.ijcesen.com/index.php/ijcesen/article/view/3306. Acesso em: 1 sep. 2025.